1. Field of the Invention
The present invention relates to electrostatic protection devices for preventing the electrostatic breakdown of protected circuits composed of semiconductor integrated circuits.
2. Description of Related Art
Semiconductor integrated circuits generally have an electrostatic protection device for preventing the breakdown of internal circuits due to electrostatic discharge (ESD) generated during LSI fabrication or LSI packaging on a board.
FIG. 6 shows the structure of a conventional electrostatic protection device, and FIG. 7 is an equivalent circuit diagram for the same. This conventional electrostatic protection device is a thyristor-type electrostatic protection device having a configuration like that of the electrostatic protection circuit disclosed in FIG. 7 of U.S. Patent Application Publication No. 2002-79538 A1 (Yuan-Mou Su, et al.).
Referring to FIG. 6, a P-type semiconductor substrate PS11 has formed on an upper face side thereof an N-type well NW11 and a P-type well PW11. Although FIG. 7 of Yuan-Mou Su et al. does not show a P-type well PW11, since the formation of a P-type well PW11 is critical to the configuration of the device, such a P-type well PW11 is shown in the example illustrated in FIG. 6.
The N-type well NW11 has formed, on an upper face side thereof, a first N+ diffusion layer ND11 and a first P+ diffusion layer PD11 which are spaced apart. The first N+ diffusion layer ND11 and the first P+ diffusion layer PD11 are connected to a signal pad. Likewise, the P-type well PW11 has formed, on an upper face side thereof, a second N+ diffusion layer ND12 and a second P+ diffusion layer PD12 which are spaced apart. The second N+ diffusion layer ND 12 is connected to a ground terminal, and the second P+ diffusion layer PD12 is connected through an external resistance RA to the ground terminal. This second P+ diffusion layer PD12 has been provided for the purpose of fixing the substrate potential.
As shown in the equivalent circuit in FIG. 7, this conventional electrostatic protection device has a PNP transistor Tr11 and an NPN transistor Tr12.
The PNP transistor Tr11 and the NPN transistor Tr12 together make up a thyristor, with the first P+ diffusion layer PD11 serving as the thyristor anode and the second N+ diffusion layer ND12 serving as the thyristor cathode. In this thyristor construction, when a voltage drop occurs at the external resistance RA due to a breakdown current generated by breakdown of the PN junction between the N-type well NW11 and the P-type well PW11, a forward bias is applied between the base and emitter of the NPN transistor Tr12, turning on the NPN transistor Tr12. Turn-on of the NPN transistor actuates the thyristor. The higher the resistance value of the external resistance RA, the lower the breakdown current at which the prescribed given voltage drop arises, enabling stable thyristor operation to be achieved.
With the conventional electrostatic protection device shown in FIG. 6, when a substrate potential fixing P+ diffusion layer PD13 formed for another device is situated nearby, the resistance Rpw between the substrate potential fixing P+ diffusion layer PD13 and the P-type well PW11 is small and so the external resistance RA ceases to function. Operation by the electrostatic protection device thus becomes unstable. To prevent such a problem from arising, a large spacing must be provided between the electrostatic protection device and the substrate potential fixing P+ diffusion layer PD13 for the other device. This essentially means that the electrostatic protection device occupies a larger surface area, which results in the semiconductor integrated circuit having a relatively large chip size.